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PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
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DTSTART:20141120T171500Z
DTEND:20141120T180000Z
LOCATION:New Orleans Theater
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: In the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore's Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while hardware designers were able to aggressively exploit instruction-level parallelism (ILP) in superscalar processors. Current multi-cores are designed as simple symmetric multiprocessors (SMP) on a chip. However, we believe that this is not enough to overcome all the problems that multi-cores face. The runtime has to drive the design of future multi-cores to overcome the restrictions in terms of power, memory, programmability and resilience that multi-cores have. In this talk, we introduce a first approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime's perspective.
SUMMARY:Runtime Aware Architectures
PRIORITY:3
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