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SCHEDULE: NOV 16-21, 2014
When viewing the Technical Program schedule, on the far righthand side is a column labeled "PLANNER." Use this planner to build your own schedule. Once you select an event and want to add it to your personal schedule, just click on the calendar icon of your choice (outlook calendar, ical calendar or google calendar) and that event will be stored there. As you select events in this manner, you will have your own schedule to guide you through the week.
Tightly Coupled Accelerators Architecture for Low-latency Inter-Node Communication Between Accelerators
SESSION: Poster Reception
EVENT TYPE: Posters
TIME: 5:15PM - 7:00PM
AUTHOR(S):Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato
ROOM:New Orleans Theater Lobby
ABSTRACT:
Inter-node communications between accelerators in heterogeneous clusters require extra latency due to the data copy between host and accelerator, and such communication latency causes severe performance degradation on applications. Especially in the next generation’s HPC systems, the strong scaling will be more serious issue than today, and the communication latency becomes the critical issue. To address this problem, we proposed the Tightly Coupled Accelerators (TCA) architecture, and designed the interconnection router chip named PEACH2. Accelerators in the TCA architecture communicate directly via the PCIe protocol to eliminate protocol overhead, as well as the data copy overhead. In this paper, we present HA- PACS/TCA system, the proof-of-concept GPU cluster based on the TCA architecture. Our system demonstrates 2.3 μsec of the latency on the inter-node GPU-to-GPU communication. As the result of Himeno benchmark, we demonstrated that TCA improves the scalability of the performance in the small size with up to 65%.
Chair/Author Details:
Toshihiro Hanawa - University of Tokyo
Yuetsu Kodama - University of Tsukuba
Taisuke Boku - University of Tsukuba
Mitsuhisa Sato - University of Tsukuba
Click here to download .ics calendar file
